In the near future new third generation (3G) mobile telephony standards, such as CDMA2000 and W-CDMA (Wideband Code Division Multiple Access) will be introduced. To keep pace, systems and devices need to be re-designed. For example, these new standards will require faster phase-locked loop (hereafter referred to as “PLL”) circuits.
Re-designing a PLL means modifying its operational characteristics. Three common operating characteristics are phase noise, reference frequency spurious suppression and settling time. (i.e., switching speed). Existing attempts to modify PLLs have focused on simultaneously improving all three operating characteristics. Unfortunately, when one characteristic is improved it has adverse affects on another. For example, improving a PLL's switching speed or settling time has adverse affects on its phase noise and reference spurious suppression.
As new, mobile terminals (e.g., wireless telephones, PDAs, etc . . . ) are deployed to meet new standards, there will be a need to provide backward compatibility with existing standards. So-called dual-band/dual-mode or tri-band/triple-mode terminals are becoming common, and will continue to proliferate. These terminals must operate using both existing (so-called second generation or “2G”) and 3G standards. The base stations which communicate with these mobile terminals have identical multi-band, multi-mode requirements. To do so PLLs present in both mobile terminals and fixed base stations must be capable of operating over a wide frequency range. Said another way, such a PLL must adjust or “re-tune” the frequency at which it is operating. The time it takes for a PLL to re-tune, however, is limited by its “loop filter bandwidth” (often also optimized for noise and spurious performance) and the maximum current available from a “charge pump” output.
Additionally, PLLs used in dual or triple band terminals or base stations may have to be re-tuned to a frequency within a given frequency band, and/or to a frequency within an entirely different band. This type of re-tuning may be several hundred megahertz (MHz) in nature and would be slowed down by phase ambiguities in the phase/frequency detector (“PFD”).
Accordingly, it is desirable to provide for devices and methods which improve a PLL's switching speed without sacrificing other operating characteristics of the PLL.
Other desires will become apparent from the drawings, detailed description of the invention and claims, which follow.